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preliminary gs81302r08/09/18/36e -333/300/250/200/167 144mb sigmaddr tm -ii burst of 4 sram 333 mhz?167 mhz 1.8 v v dd 1.8 v and 1.5 v i/o 165-bump bga commercial temp industrial temp rev: 1.01a 6/2010 1/36 ? 2007, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? simultaneous read and write sigmaddr? interface ? common i/o bus ? jedec-standard pinout and package ? double data rate interface ? byte write (x36 and x18) an d nyb b le write (x8) function ? burst of 4 read and write ? 1.8 v +100/?100 mv core power supply ? 1.5 v or 1.8 v hstl interface ? pipelined read operation with self-timed late write ? fully coherent read and write pipelines ? zq pin for programmable output drive strength ? ieee 1149.1 jtag-compliant boundary scan ? pin-compatible with present 9mb, 18mb, 36mb and 72mb devi ces ? 165-bump, 15 mm x 17 mm, 1 mm bump pitch bga package ? rohs-compliant 165-bump bga package available sigmaddr ? family overview the gs81302r08/09/18/36e are built in compliance with the sigmaddr-ii sram pinout standard for common i/o synchronous srams. they are 150,994,944-bit (144mb) srams. the gs81302r08/09/18/36e sigmaddr-ii srams are just one element in a fami ly of low power, low voltage hstl i/o srams designed to operate at the speeds needed to implement economical high perf ormance networking systems. clocking and addressing schemes the gs81302r08/09/18/36e sigmaddr-ii srams are synchronous devices. they employ two input register clock inputs, k and k . k and k are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. the device also allows the user to manipulate the output register clock inputs quasi independently with the c and c clock inputs. c and c are also independent single-ended clock inputs, not differential inputs. if the c clocks are tied high, the k clocks are routed internally to fire the output registers instead. common i/o x36 and x18 sigmaddr-ii b4 rams always transfer data in four packets. when a new address is loaded, a0 and a1 preset an internal 2 bit linear address counter. the counter increments by 1 for each b eat of a burst of four data transfer. the counter always wr aps to 00 after reaching 11, no matter where it starts. common i/o x8 and x9 sigmaddr-ii b4 rams always transfer data in four packets. when a new address is loaded, the lsbs are internally set to 0 for the first read or write transfer, and incremented by 1 for the next 3 transfers. because the lsbs are tied off inte rnally, the address field of a x8/x9 sigmaddr-ii b4 ram is always two address pins less than the advertised index depth (e.g., the 16m x 9 has a 4m addressable index). parameter synopsis -333 -300 -250 -200 -167 tkhkh 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns tkhqv 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.5 ns 165-bump, 15 mm x 17 mm bga 1 mm bump pitch, 11 x 15 bump array bottom view
4m x 36 sigmaddr-ii sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa r/ w bw2 k bw1 ld sa sa cq b nc dq27 dq18 sa bw3 k bw0 sa nc/sa (288mb) nc dq8 c nc nc dq28 v ss sa sa0 sa1 v ss nc dq17 dq7 d nc dq29 dq19 v ss v ss v ss v ss v ss nc nc dq16 e nc nc dq20 v ddq v ss v ss v ss v ddq nc dq15 dq6 f nc dq30 dq21 v ddq v dd v ss v dd v ddq nc nc dq5 g nc dq31 dq22 v ddq v dd v ss v dd v ddq nc nc dq14 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc dq32 v ddq v dd v ss v dd v ddq nc dq13 dq4 k nc nc dq23 v ddq v dd v ss v dd v ddq nc dq12 dq3 l nc dq33 dq24 v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc dq34 v ss v ss v ss v ss v ss nc dq11 dq1 n nc dq35 dq25 v ss sa sa sa v ss nc nc dq10 p nc nc dq26 sa sa c sa sa nc dq9 dq0 r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm 2 body?1 mm bump pitch notes: 1. bw0 controls writes to dq0:dq8; bw1 controls writes to dq9:dq17; bw2 controls writes to dq18:dq26; bw3 controls writes to dq27:dq35. 2. b9 is the expansion address. preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 2/36 ? 2007, gsi technology
8m x 18 sigmaddr-ii sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa r/ w bw1 k sa ld sa sa cq b nc dq9 nc sa nc/sa (288mb) k bw0 sa nc nc dq8 c nc nc nc v ss sa sa0 sa1 v ss nc dq7 nc d nc nc dq10 v ss v ss v ss v ss v ss nc nc nc e nc nc dq11 v ddq v ss v ss v ss v ddq nc nc dq6 f nc dq12 nc v ddq v dd v ss v dd v ddq nc nc dq5 g nc nc dq13 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq4 nc k nc nc dq14 v ddq v dd v ss v dd v ddq nc nc dq3 l nc dq15 nc v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc nc v ss v ss v ss v ss v ss nc dq1 nc n nc nc dq16 v ss sa sa sa v ss nc nc nc p nc nc dq17 sa sa c sa sa nc nc dq0 r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm 2 body?1 mm bump pitch notes: 1. bw0 controls writes to dq0:dq8; bw1 controls writes to dq9:dq17. 2. b5 is the expansion address. preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 3/36 ? 2007, gsi technology
16m x 9 sigmaddr-ii sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa r/ w nc k sa ld sa sa cq b nc nc nc sa nc/sa (288mb) k bw0 sa nc nc dq4 c nc nc nc v ss sa nc sa v ss nc nc nc d nc nc nc v ss v ss v ss v ss v ss nc nc nc e nc nc dq5 v ddq v ss v ss v ss v ddq nc nc dq3 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc nc dq6 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq2 nc k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc dq7 nc v ddq v ss v ss v ss v ddq nc nc dq1 m nc nc nc v ss v ss v ss v ss v ss nc nc nc n nc nc nc v ss sa sa sa v ss nc nc nc p nc nc dq8 sa sa c sa sa nc nc dq0 r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm 2 body?1 mm bump pitch notes: 1. unlike the x36 and x18 versions of this device, t he x8 and x9 versions do not give the user access to a0 and a1. sa0 and sa1 are set to 0 at the beginning of each access. 2. bw0 controls writes to dq0:dq8. 3. b5 is the expansion address. preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 4/36 ? 2007, gsi technology
16m x 8 sigmaddr-ii sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa r/ w nw1 k sa ld sa sa cq b nc nc nc sa nc/sa (288mb) k nw0 sa nc nc dq3 c nc nc nc v ss sa nc sa v ss nc nc nc d nc nc nc v ss v ss v ss v ss v ss nc nc nc e nc nc dq4 v ddq v ss v ss v ss v ddq nc nc dq2 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc nc dq5 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq1 nc k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc dq6 nc v ddq v ss v ss v ss v ddq nc nc dq0 m nc nc nc v ss v ss v ss v ss v ss nc nc nc n nc nc nc v ss sa sa sa v ss nc nc nc p nc nc dq7 sa sa c sa sa nc nc nc r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm 2 body?1 mm bump pitch notes: 1. unlike the x36 and x18 versions of this device, t he x8 and x9 versions do not give the user access to a0 and a1. sa0 and sa1 are set to 0 at the beginning of each access. 2. nw0 controls writes to dq0:dq3; nw1 controls writes to dq4:dq7. 3. b5 is the expansion address. preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 5/36 ? 2007, gsi technology
pin description table symbol description type comments sa synchronous address inputs input ? r/ w synchronous read/write input read: active high write: active low bw0 ? bw3 synchronous byte writes input active low x18/x36 only nw0 ? nw1 nybble write control pin input active low x8 only ld synchronous load pin input active low k input clock input active high k input clock input active low c output clock input active high c output clock input active low tms test mode select input ? tdi test data input input ? tck test clock input input ? tdo test data output output ? v ref hstl input reference voltage input ? zq output impedance matching input input ? mcl must connect low ? ? dq data i/o input/output three state doff disable dll when low input active low cq output echo clock output ? cq output echo clock output ? v dd power supply supply 1.8 v nominal v ddq isolated output buffer supply supply 1.8 v or 1.5 v nominal v ss power supply: ground supply ? nc no connect ? ? preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 6/36 ? 2007, gsi technology note: nc = not connected to die or any other pin
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 7/36 ? 2007, gsi technology background common i/o srams, from a system architectur e point of view, are attractiv e in read dominated or bl ock transfer applications. therefore, the sigmaddr-ii sram interf ace and truth table are optimized for burs t reads and writes. common i/o srams are unpopular in applications where alternating reads and writes are needed because bus turn around delays can cut high speed common i/o sram data bandwidth in half. burst operations read and write operations are ?burst? oper ations. in every case where a read or write command is accepted by the sram, it will respond by issuing or accepting four beats of data, executing a data transfer on subsequent rising edges of k and k#, as illust rated in the timing diagrams. it is not possible to stop a burst once it starts. four beats of data ar e always transferred. this mean s that it is possible to load new addresses every other k clock cycle. addresses can be loaded less often, if intervening deselect cycles ar e inserted. deselect cycles chip deselect commands are pipelined to the same degree as read commands. this means th at if a deselect command is applied to the sram on the next cycle after a read co mmand captured by the sram, th e device will complete the four beat read data transfer and then execute the deselect command, returning the output drivers to high-z.a high on the ld# pin prevents the ram from loading read or write command inputs and puts the ram into dese lect mode as soon as it completes all outstanding burst transfer operations. sigmaddr-ii burst of 4 sram read cycles the status of the address, ld# and r/w# pins are evaluated on the rising edge of k. because the device execu tes a four beat bur st transfer in response to a r ead command, if the previous command captured was a read or write command, the address, ld and r/ w pins are ignored. if the previous comm and captured was a deselect, the control pi n status is checked.the sram executes pipelined reads. the read command is clocked into the sram by a rising edge of k. afte r the next rising edge of k, the sram produces data out in response to the next rising edge of c (or the next rising edge of k , if c and c are tied high). the second beat of data is transferred on the next rising edge of c, then on the next rising edge of c and finally on the next rising edge of c, for a total of four transfers per address load. sigmaddr-ii burst of 4 sram write cycles the status of the address, ld and r/ w pins are evaluated on the rising edge of k. because the device executes a four beat burst transfer in response to a writ e command, if the previous co mmand captured was a read or write command, the address, ld and r/ w pins are ignored at the next rising edge of k. if the previous command captured was a deselect, the control pin status is checked.the sram executes ?late write? data tr ansfers. data in is due at the device in puts on the rising edge of k following th e rising edge of k clock used to clock in th e write command and the write address. to co mplete the remaining three beats of the b urst of four write transfer th e sram captures data in on the next rising edge of k , the following rising edge of k and finally on the next rising edge of k , for a total of four tr ansfers per address load.
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 8/36 ? 2007, gsi technology power-up sequence for sigmaddr-ii srams sigmaddr-ii srams must be powered-up in a specific sequence in order to avoid undefined operations. power-up sequence 1. power-up and maintain doff at low state. 1a. apply v dd . 1b. apply v ddq . 1c. apply v ref (may also be applied at the same time as v ddq ). 2. after power is achieved and clocks (k, k , c, c ) are stablized, change doff to high. 3. an additional 1024 clock cycl es are required to lock the dll after it has been enabled. note: the dll may be reset by driving the doff pin low or by stopping the k clocks fo r at least 30 ns. 1024 cycles of clean k clocks are always required to re- lock the dll after reset. dll constraints ? the dll synchronizes to either k or c clock. these clocks should have low phase jitter (t kcvar ). ? the dll cannot operate at a frequency lower tha n that specified by the t khkh maximum specification for the desi red operating clock frequency. ? if the incoming clock is not stablized when dll is enabled, the dll may lock on th e wrong frequency and cause undefined errors or failures during the initial stage. note: if the frequency is changed, dll reset is required. after reset, a minimum of 1024 cycles is required for dll lock. special functions byte write and nybble write control byte write enable pins are sampled at the same time that data in is sam pl ed. a high on the byte write enable pin associated wit h a particular byte (e.g., bw0 controls d0?d8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. a ny or all of the byte write enable pins may be driven high or low during the data in sample times in a write sequence. each write enable command and write addres s loaded into the ram provides the base ad dress for a 4 beat data transfer. the x18 version of the ram, for example, may write 72 bits in associatio n with each address loaded. any 9-bit byte may be masked in any write sequence. nybble write (4-bit) write control is implemented on the 8-bit-wi de versi on of the device. for the x8 version of the device, ?nybble write enable? and ? nbx ? may be substituted in all the discussion above. example x18 ram write sequence using byte write enables data in sample time bw0 bw1 d0?d8 d9?d17 beat 1 0 1 data in don?t care beat 2 1 0 don?t care data in beat 3 0 0 data in data in beat 4 1 0 don?t care data in resulting write operation byte 1 d0?d8 byte 2 d9?d17 byte 1 d0?d8 byte 2 d9?d17 byte 1 d0?d8 byte 2 d9?d17 byte 1 d0?d8 byte 2 d9?d17 written unchanged unchanged written written written unchanged written beat 1 beat 2 beat 3 beat 4
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 9/36 ? 2007, gsi technology output register control sigmaddr-ii srams offer two mechanisms for controlling the output dat a registers. typically, control is handled by the output register clock inputs, c and c . the output register clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of th e k and k clocks. if the c and c clock inputs isare tied high, the ram reverts to k and k control of the outputs, allowing the ram to function as a conventional pipelined read sram. flxdrive-ii output driver impedance control hstl i/o sigmaddr-ii srams are supplied with programmable impe dan ce output drivers. the zq pin must be connected to v ss via an external resistor, rq, to allow th e sram to monitor and adjust its output driver impedance. the value of rq must be 5x the value of the desired ram output impedance at mid-rail. the allowable range of rq to guarantee impedance matching continuously is between 175 and 350 . periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and te mperature. the sram?s output impedance ci rcuitry compensates for drifts in supply voltage and temperature. a clock cycle count er periodically triggers an impedance eval uation, resets and co unts again. each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. the output drivers implemented with discrete binary weighted impedance st eps is implemented with discrete binary weighted impedance steps.
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 10/36 ? 2007, gsi technology example four bank depth expansion schematic a k r/w ld a 0 ?a n k bank 0 bank 1 bank 2 bank 3 a k ld a k ld a k ld r/w r/w r/w dq dq dq dq cc cc dq1?dqn c r/w ld 0 ld 1 ld 2 ld 3 note: for simplicity bwn (or nwn) , k , and c are not shown. cq cq cq cq cq common i/o sigmaddr-ii burs t of 4 sram truth table k n ld r/ w dq operation a + 0 a + 1 a + 2 a + 3
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 11/36 ? 2007, gsi technology 1 x hi-z hi-z hi-z hi-z deselect 0 0 d@k n+1 d@ k n+1 d@k n+2 d@ k n+2 write 0 1 q@ k n+1 or c n+1 q@k n+2 or c n+2 q@ k n+2 or c n+2 q@k n+3 or c n+3 read note: q is controlled by k clocks if c clocks are n ot used. burst of 4 byte writ e clock truth table bw bw bw bw current operation d d d d k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) k (t n ) k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) t t t t write dx stored if bwn = 0 in all four data transfers d0 d2 d3 d4 t f f f write dx stored if bwn = 0 in 1st data transfer only d0 x x x f t f f write dx stored if bwn = 0 in 2nd data transfer only x d1 x x f f t f write dx stored if bwn = 0 in 3rd data transfer only x x d2 x f f f t write dx stored if bwn = 0 in 4th data transfer only x x x d3 f f f f write abort no dx stored in any of the four data transfers x x x x notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 2. if one or more bwn = 0, then bw = ?t?, else bw = ?f?. common i/o sigmaddr-ii burs t of 4 sram truth table
burst of 4 nybble write clock truth table nw nw nw nw current operation d d d d k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) k (t n ) k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) t t t t write dx stored if nwn = 0 in all four data transfers d0 d2 d3 d4 t f f f write dx stored if nwn = 0 in 1st data transfer only d0 x x x f t f f write dx stored if nwn = 0 in 2nd data transfer only x d1 x x f f t f write dx stored if nwn = 0 in 3rd data transfer only x x d2 x f f f t write dx stored if nwn = 0 in 4th data transfer only x x x d3 f f f f write abort no dx stored in any of the four data transfers x x x x notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 2. if one or more nwn = 0, then nw = ?t?, else nw = ?f?. preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 12/36 ? 2007, gsi technology
x36 byte write enable ( bwn ) truth table bw0 bw1 bw2 bw3 d0?d8 d9?d17 d18?d26 d27?d35 1 1 1 1 don?t care don?t care don?t care don?t care 0 1 1 1 data in don?t care don?t care don?t care 1 0 1 1 don?t care data in don?t care don?t care 0 0 1 1 data in data in don?t care don?t care 1 1 0 1 don?t care don?t care data in don?t care 0 1 0 1 data in don?t care data in don?t care 1 0 0 1 don?t care data in data in don?t care 0 0 0 1 data in data in data in don?t care 1 1 1 0 don?t care don?t care don?t care data in 0 1 1 0 data in don?t care don?t care data in 1 0 1 0 don?t care data in don?t care data in 0 0 1 0 data in data in don?t care data in 1 1 0 0 don?t care don?t care data in data in 0 1 0 0 data in don?t care data in data in 1 0 0 0 don?t care data in data in data in 0 0 0 0 data in data in data in data in x18 byte write enable ( bwn ) truth table bw0 bw1 d0?d8 d9?d17 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in x8 nybble write enable ( nwn ) truth table nw0 nw1 d0?d3 d4?d7 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 13/36 ? 2007, gsi technology
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 14/36 ? 2007, gsi technology burst of 4 state diagram power-up nop load new address ddr read ddr write load read write load load load load notes: 1. the internal burst address count er is a 4-bit linear counter (i.e., when first address is a0, next internal burst address is a0+1). 2. ?read? refers to read active status with r/w = high, ?write? refers to write inactive status with r/w = low. 3. ?load? refers to read new address active status with ld = low, ?load ? refers to read new address inactive status with ld = high. load increment read address increment write address always always read write
absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.9 v v ddq voltage in v ddq pins ?0.5 to v dd v v ref voltage in v ref pins ?0.5 to v ddq v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 2.9 v max.) v v in voltage on other input pins ?0.5 to v ddq +0.5 ( 2.9 v max.) v i in input current on any pin +/?100 ma dc i out output current on any i/o pin +/?100 ma dc t j maximum junction temperature 125 o c t stg storage temperature ?55 to 125 o c note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operati on should be restricted to recomm ended operating conditions. exposure to conditi ons exceeding the recommended operating condi tions, for an extended period of time, ma y affect reliability of this component. preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 15/36 ? 2007, gsi technology recommended oper ating conditions power supplies parameter symbol min. typ. max. unit supply voltage v dd 1.7 1.8 1.9 v i/o supply voltage v ddq 1.4 ? v dd v reference voltage v ref 0.68 ? 0.95 v notes: 1. unless otherwise noted, all perfo rmance sp ecifications quoted are eva luated for worst case at both 1.4 v v ddq 1.6 v (i.e., 1.5 v i/o) and 1.7 v v ddq 1.9 v (i.e., 1.8 v i/o) and quoted at whichever condition is worst case. 2. the power supplies need to be powered up simu ltane ously or in the following seq uence: v dd , v ddq , v ref , followed by signal inputs. the power down sequence must be the reverse. v ddq must not exceed v dd .. operating temperature parameter symbol min. typ. max. unit ambient temperature (commercial range versions) t a 0 25 70 c ambient temperature (industrial range versions) t a ?40 25 85 c
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 16/36 ? 2007, gsi technology hstl i/o dc input characteristics parameter symbol min max units notes dc input logic high v ih (dc) v ref + 0.10 v ddq + 0.3 v v 1 dc input logic low v il (dc) ?0.3 v v ref ? 0.10 v 1 notes: 1. compatible with both 1.8 v and 1.5 v i/o drivers 2. these are dc test criteria . dc design criteria is v ref 50 mv. the ac v ih /v il levels are defined separatel y for measuring timing parame - ters. 3. v il (min) dc = ?0.3 v, v il (min) ac = ?1.5 v (pulse width 3 ns). 4. v ih (max) dc = v ddq + 0.3 v, v ih (max) ac = v ddq + 0.85 v (pulse width 3 ns). hstl i/o ac input characteristics parameter symbol min max units notes ac input logic high v ih (ac) v ref + 0.20 ? v 2,3 ac input logic low v il (ac) ? v ref ? 0.20 v 2,3 v ref peak-to-peak ac voltage v ref (ac) ? 5% v ref (dc) v 1 notes: 1. the peak-to-peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2. to guarantee ac characteristics, v ih ,v il , trise, and tfall of inputs and clocks must be within 10% of each other. 3. for devices supplied with hstl i/o input buffers . compatible with both 1.8 v and 1.5 v i/o drivers. 20% tkhkh v ss ? 1.0 v 50% v ss v ih undershoot measurement and timing overshoot measure ment and timing 20% tkhkh v dd + 1.0 v 50% v dd v il capacitance o c, f = 1 mh z , v dd = 1.8 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf output capacitance c out v out = 0 v 6 7 pf clock capacitance c clk ? 5 6 pf note: this parameter is sample tested. (t a = 25
ac test conditions parameter conditions input high level v ddq input low level 0 v max. input slew rate 2 v/ns input reference level v ddq /2 output reference level v ddq /2 note: test conditions as specified with output loading as shown unl ess otherwise noted. preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 17/36 ? 2007, gsi technology dq vt = v ddq /2 50 rq = 250 (hstl i/o) v ref = 0.75 v ac test load diagram input and output leakage characteristics parameter symbol test conditions min. max input leakage current (except mode pins) i il v in = 0 to v ddq ?2 ua 2 ua doff i il doff v in = 0 to v ddq ?20 ua 2 ua output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 18/36 ? 2007, gsi technology programmable impedance hstl output driver dc electrical characteristics parameter symbol min. max. units notes output high voltage v oh1 v ddq /2 v ddq v 1, 3 output low voltage v ol1 vss v ddq /2 v 2, 3 output high voltage v oh2 v ddq ? 0.2 v ddq v 4, 5 output low voltage v ol2 vss 0.2 v 4, 6 notes: 1. i oh = (v ddq /2) / (rq/5) +/? 15% @ v oh = v ddq /2 (for: 175 rq 350 ). 2. i ol = (v ddq /2) / (rq/5) +/? 15% @ v ol = v ddq /2 (for: 175 rq 350) . 3. parameter tested with rq = 250 and v ddq = 1.5 v or 1.8 v 4. 0 rq ? 5. i oh = ?1.0 ma 6. i ol = 1.0 ma operating currents parameter symbol test conditions -333 -300 -250 -200 -167 notes 0 to 70c ?40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c operat ing current (x36): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 2, 3 operating current (x18): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 2, 3 operating current (x9): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 2, 3 operating current (x8): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 2, 3 standby current (nop): ddr i sb1 device deselected, i out = 0 ma, f = max, all inputs 0.2 v or v dd ? 0.2 v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 2, 4 notes: 1. power measured with output pins floating. 2. minimum cycle, i out = 0 ma 3. operating current is calculated wi t h 50% re ad cycles and 50% write cycles. 4. standby current is only after all pending re ad and writ e burst operations are completed.
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 19/36 ? 2007, gsi technology ac electrical characteristics parameter symbol -333 -300 -250 -200 -167 units notes min max min max min max min max min max clock k, k clock cycle time c, c clock cycle time t khkh t chch 3.0 4.5 3.3 4.5 4.0 8.4 5.0 8.4 6.0 8.4 ns tkc variable t kcvar ? 0.2 ? 0.2 ? 0.2 ? 0.2 ? 0.2 ns 6 k, k clock high pulse width c, c clock high pulse width t khkl t chcl 1.2 ? 1.32 ? 1.6 ? 2.0 ? 2.4 ? ns k, k clock low pulse width c, c clock low pulse width t klkh t clch 1.2 ? 1.32 ? 1.6 ? 2.0 ? 2.4 ? ns k to k high c to c high t kh k h t ch c h 1.35 ? 1.49 ? 1.8 ? 2.2 ? 2.7 ? ns k to k high c to c high t k hkh t c hch 1.35 ? 1.49 ? 1.8 ? 2.2 ? 2.7 ? ns k, k clock high to c, c clock high t khch 0 0.8 0 0.8 0 1.8 0 2.3 0 2.8 ns dll lock time t kclock 1024 ? 1024 ? 1024 ? 1024 ? 1024 ? cycle 6 k static to dll reset t kcreset 30 ? 30 ? 30 ? 30 ? 30 ? ns output times k, k clock high to data output valid c, c clock high to data output valid t khqv t chqv ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.5 ns 4 k, k clock high to data output hold c, c clock high to data output hold t khqx t chqx ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.5 ? ns 4 k, k clock high to echo clock valid c, c clock high to echo clock valid t khcqv t chcqv ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.5 ns k, k clock high to echo clock hold c, c clock high to echo clock hold t khcqx t chcqx ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.5 ? ns cq, cq high output valid t cqhqv ? 0.25 ? 0.27 ? 0.30 ? 0.35 ? 0.40 ns 8 cq, cq high output hold t cqhqx ?0.25 ? ?0.27 ? ?0.30 ? ?0.35 ? ?0.40 ? ns 8 cq phase distortion t cqh cq h t cq hcqh 1.10 ? 1.24 ? 1.55 ? 1.95 ? 2.45 ? ns k clock high to data output high-z c clock high to data output high-z t khqz t chqz ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.5 ns 4 k clock high to data output low-z c clock high to data output low-z t khqx1 t chqx1 ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.5 ? ns 4 setup times address input setup time t avkh 0.4 ? 0.4 ? 0.5 ? 0.6 ? 0.7 ? ns 1 control input setup time(r/ w ) ( ld ) t ivkh 0.4 ? 0.4 ? 0.5 ? 0.6 ? 0.7 ? ns 2 control input setup time ( bwx ) ( nwx ) t ivkh 0.28 ? 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns 3 data input setup time t dvkh 0.28 ? 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 20/36 ? 2007, gsi technology hold times address input hold time t khax 0.4 ? 0.4 ? 0.5 ? 0.6 ? 0.7 ? ns 1 control input hold time (r/ w ) ( ld ) t khix 0.4 ? 0.4 ? 0.5 ? 0.6 ? 0.7 ? ns 2 control input hold time ( bwx ) ( nwx ) t khix 0.28 ? 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns 3 data input hold time t khdx 0.28 ? 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns notes: 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. control singles are r/ w , ld . 3. control singles are bw0 , bw1 , and ( nw0 , nw1 for x8) and ( bw2 , bw3 for x36). 4. if c, c are tied high, k, k become the references for c, c timing parameters 5. to avoid bus contention, at a given volt age and temperature tchqx1 is bigger than t chqz. the specs as shown do not imply bus contention because tchqx1 is a min parameter that is worst case at totally different test conditions (0 c, 1.9 v) than tchqz, which is a max parameter (worst case at 70 c, 1.7 v). it is not possible for two srams on the same board to be at such different voltages and temperatures. 6. clock phase jitter is the variance from clock ri sing edge to the next expected clock rising edge. 7. v dd slew rate must be less than 0.1 v dc per 50 ns for dll lock retention. dll lock time begins once v dd and input clock are stable. 8. echo clock is very tightly controlled to data valid/data hold. by des ign, there is a 0.1 ns variation from echo clock to dat a. the datasheet parameters reflect tester guard bands and test setup variations. ac electrical character istics (continued) parameter symbol -333 -300 -250 -200 -167 units notes min max min max min max min max min max
c and c controlled read first timing diagram read a cont read a nop write b cont write b read c a b c b b+1 b+2 b+3 a a+1 a+2 a+3 b b+1 b+2 b+3 cqhqx cqhqv chcqv chcqx chcqv chcqx khdx dvkh chqz chqv chqx chqx1 khnkh klkhklkh khklkhkl khkhkhkh khix ivkh khix ivkh khix ivkh khax avkh khnkh klkhklkh khklkhkl khkhkhkh k k address ld r/w bwx c c dq cq cq preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 21/36 ? 2007, gsi technology
k and k controlled read first timing diagram read a cont read a nop write b cont write b read c a b c b b+1 b+2 b+3 a a+1 a+2 a+3 b b+1 b+2 b+3 cqhqx cqhqv chcqv chcqx chcqv chcqx khdx dvkh khqz khqv khqx khqx1 khix ivkh khix ivkh khix ivkh khax avkh kh#kh klkhklkh khklkhkl khkhkhkh k k address ld r/w bwx dq cq cq preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 22/36 ? 2007, gsi technology
c and c controlled write first timing diagram write a cont write a read b cont read b nop write c cont write c a b c a a+1 a+2 a+3 c c+1 c+2 a a+1 a+2 a+3 b b+1 b+2 b+3 c c+1 cqhqx cqhqv chcqv chcqx chqz chqx chqv chqx1 khdx dvkh khnkh klkhklkh khklkhkl khkhkhkh khix ivkh khix ivkh khix ivkh khax avkh khnkh klkhklkh khklkhkl khkhkhkh k k address ld r/w c c dq cq cq bwx preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 23/36 ? 2007, gsi technology
k and k controlled write first timing diagram nop write a read b read c nop write d nop b b+1 c c+1 cqhqx cqhqv khcqv khcqx khcqv khqx khqv khqx1 khdx dvkh khix ivkh khix ivkh khix ivkh khax avkh khnkh klkhklkh khklkhkl khkhkhkh k k address ld w r/ bwx dq cq cq write a1 cont write a read b cont read b nop write c cont write c khnkh klkhklkh khklkhkl khkhkhkh k k preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 24/36 ? 2007, gsi technology
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 25/36 ? 2007, gsi technology jtag port operation overview the jtag port on this ram operates in a manner that is compliant with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag). the jtag port input inte rface levels scale with v dd . the jtag output drivers are powered by v dd . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all i nputs are captured on the rising edge of tck and a ll outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is t he command input for the t ap controller state machine. an undriven tms input wi ll produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers pla c ed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controll er state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state o f the tap state machine. output changes in response to the falling edge of tck. this is the out put side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ie ee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset automaticly at power-up. jtag port registers overview the various jtag registers, refered to as tes t access port or ta p registers, are selected (one at a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of the tap regist ers is a serial shift register that captures serial input data o n the rising edge of tck and pushes serial data out on the next falling edge of tck. when a register is selected, it is placed betwe en the tdi and tdo pins. instruction register the instruction register holds the instructi ons that are executed by the ta p controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. th e instruction register can be lo aded when it is placed betwee n the tdi and tdo pins. the instruction register is automatically preloa ded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed th rough the ram?s jtag port to another device in the scan chain with as little delay as possible.
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 26/36 ? 2007, gsi technology boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pin s . the flip flops are then daisy chained togeth er so the levels found can be shifted seri ally out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip fl ops (always set to a logic 1). the relationship between t he device pins and the bits in the boundary scan register is described in the scan order table following. the boundary scan register, under the control of the tap contro ller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. sample-z, sample/preload and extest instructions can be us ed to activate the boundary scan register. instruction register id code register boundary scan register 012 0 31 30 29 1 2 0 bypass register tdi tdo tms tck test access port (tap) controller 108 1 0 control signals jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction re gister. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when th e controller is moved into shift- dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins.
id register contents see bsdl model gsi technology jedec vendor id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x x x x x x x x x x 0 0 0 1 1 0 1 1 0 0 1 1 preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 27/36 ? 2007, gsi technology tap controller instruction set overview there are two classes of instructions defined in the standard 114 9.1-1 990; the standard (public) instructions, and device speci fic (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on th is device may be used to monitor all inpu t and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in captur e-ir s t ate the two least significant bits of the instruction regi ster are loaded wit h 01. when the controller is moved to the shift-ir state the instruction register is placed between tdi and tdo. in this state the de sired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions , the tap executes newly loaded instruct ions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table.
select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 10 0 0 1 11 1 preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 28/36 ? 2007, gsi technology jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass regi ster is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facili - tate testing of other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public in stru ction . when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. boundary scan regist er locations are not associated with an input or i/o pin, and are loaded with the default stat e identified in the boundary s can chain table at the end of th is section of the datasheet. beca use the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs w ill not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set-up plus hold time (tts plus tth) . the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary s can register. moving the contro ller to shift-dr state then places the boundary scan register between the tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instru ction register is loaded with all logic 0s. the extest command does not block or override th e ram?s input pins; therefore, the ram?s internal state is still determined by its input pins.
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 29/36 ? 2007, gsi technology typically, the boundary scan re gister is loaded with the desired pattern of data with the sample/preload command. then the extest command is used to outp ut the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling edge of tck when the controller is in the update-ir state. alternately, the boundary scan register ma y be loaded in parallel using the extest command. when the extest instruc - tion is selected, the sate of all the ram?s input and i/o pins, as well as the defau lt val ues at scan register locations not as so - ciated with a pin, are transfer red in parallel into the boundary scan regist er on the rising edge of tck in the capture-dr state, the ram?s output pins drive out the value of the boundar y scan register location with which each output pin is associ - ated. idcode the idcode instruction causes the id rom to be loaded into the id registe r when the controller is in capture-dr mode and places the id register between the tdi a nd tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the ins t ruction register, all ram outputs are forced to an inactiv e drive state (high- z) and the boundary scan register is connected between tdi and t do when the tap controller is moved to the shift-dr state. jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan register between tdi and tdo. 1 idcode 001 preloads id register and plac es it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the b o undary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 gsi 011 gsi private instruction. 1 sample/preload 100 captures i/o ring contents. places the b o undary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 gsi 110 gsi private instruction. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 30/36 ? 2007, gsi technology jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes test port input low voltage v ilj ? 0.3 0.3 * v dd v 1 test port input high voltage v ihj 0.7 * v dd v dd +0.3 v 1 tms, tck and tdi input leakage current i inhj ? 300 1 ua 2 tms, tck and tdi input leakage current i inlj ? 1 100 ua 3 tdo output leakage current i olj ? 1 1 ua 4 test port output high voltage v ohj v dd ? 0.2 ? v 5, 6 test port output low voltage v olj ? 0.2 v 5, 7 test port output cmos high v ohjc v dd ? 0.1 ? v 5, 8 test port output cmos low v oljc ? 0.1 v 5, 9 notes: 1. input under/overshoot voltage must be ? 1 v < vi < v ddn +1 v not to exceed 2.9 v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj v in v ddn 3. 0 v v in v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v dd supply. 6. i ohj = ? 2 ma 7. i olj = + 2 ma 8. i ohjc = ?100 ua 9. i oljc = +100 ua notes: 1. include scope and jig capacitance. 2. test conditions as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v dd /2 tdo v dd /2 50 30pf * jtag port ac test load * distributed test jig capacitance
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 31/36 ? 2007, gsi technology jtag port timing diagram tth tts ttkq tth tts tth tts ttklttkl ttkhttkh ttkcttkc tck tdi tms tdo parallel sram input jtag port ac electri cal characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 32/36 ? 2007, gsi technology package dimensions?165-bump fpbga (package e) a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 a1 corner top view a1 corner bottom view 1.0 1.0 10.0 1.0 1.0 14.0 150.05 170.05 a b 0.20(4x) ?0.10 ?0.25 c c a b m m ?0.40~0.60 (165x) c seating plane 0.15 c 0.36~0.46 1.50 max.
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 33/36 ? 2007, gsi technology ordering information?gsi sigmaddr-ii sram org part number1 type package speed (mhz) t a 2 16m x 8 gs81302r08e-333 sigmaddr-ii b4 sram 165-bump bga 333 c 16m x 8 gs81302r08e-300 sigmaddr-ii b4 sram 165-bump bga 300 c 16m x 8 gs81302r08e-250 sigmaddr-ii b4 sram 165-bump bga 250 c 16m x 8 gs81302r08e-200 sigmaddr-ii b4 sram 165-bump bga 200 c 16m x 8 gs81302r08e-167 sigmaddr-ii b4 sram 165-bump bga 167 c 16m x 8 gs81302r08e-333i sigmaddr-ii b4 sram 165-bump bga 333 i 16m x 8 gs81302r08e-300i sigmaddr-ii b4 sram 165-bump bga 300 i 16m x 8 gs81302r08e-250i sigmaddr-ii b4 sram 165-bump bga 250 i 16m x 8 GS81302R08E-200I sigmaddr-ii b4 sram 165-bump bga 200 i 16m x 8 gs81302r08e-167i sigmaddr-ii b4 sram 165-bump bga 167 i 16m x 9 gs81302r09e-333 sigmaddr-ii b4 sram 165-bump bga 333 c 16m x 9 gs81302r09e-300 sigmaddr-ii b4 sram 165-bump bga 300 c 16m x 9 gs81302r09e-250 sigmaddr-ii b4 sram 165-bump bga 250 c 16m x 9 gs81302r09e-200 sigmaddr-ii b4 sram 165-bump bga 200 c 16m x 9 gs81302r09e-167 sigmaddr-ii b4 sram 165-bump bga 167 c 16m x 9 gs81302r09e-333i sigmaddr-ii b4 sram 165-bump bga 333 i 16m x 9 gs81302r09e-300i sigmaddr-ii b4 sram 165-bump bga 300 i 16m x 9 gs81302r09e-250i sigmaddr-ii b4 sram 165-bump bga 250 i 16m x 9 gs81302r09e-200i sigmaddr-ii b4 sram 165-bump bga 200 i 16m x 9 gs81302r09e-167i sigmaddr-ii b4 sram 165-bump bga 167 i 8m x 18 gs81302r18e-333 sigmaddr-ii b4 sram 165-bump bga 333 c 8m x 18 gs81302r18e-300 sigmaddr-ii b4 sram 165-bump bga 300 c 8m x 18 gs81302r18e-250 sigmaddr-ii b4 sram 165-bump bga 250 c 8m x 18 gs81302r18e-200 sigmaddr-ii b4 sram 165-bump bga 200 c 8m x 18 gs81302r18e-167 sigmaddr-ii b4 sram 165-bump bga 167 c 8m x 18 gs81302r18e-333i sigmaddr-ii b4 sram 165-bump bga 333 i 8m x 18 gs81302r18e-300i sigmaddr-ii b4 sram 165-bump bga 300 i 8m x 18 gs81302r18e-250i sigmaddr-ii b4 sram 165-bump bga 250 i 8m x 18 gs81302r18e-200i sigmaddr-ii b4 sram 165-bump bga 200 i 8m x 18 gs81302r18e-167i sigmaddr-ii b4 sram 165-bump bga 167 i 4m x 36 gs81302r36e-333 sigmaddr-ii b4 sram 165-bump bga 333 c notes: 1. for tape and reel add the character ?t? to the end of the part number . example: gs81302r36e-300t. 2. c = commercial temperature range. i = industrial t emperature range.
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 34/36 ? 2007, gsi technology 4m x 36 gs81302r36e-300 sigmaddr-ii b4 sram 165-bump bga 300 c 4m x 36 gs81302r36e-250 sigmaddr-ii b4 sram 165-bump bga 250 c 4m x 36 gs81302r36e-200 sigmaddr-ii b4 sram 165-bump bga 200 c 4m x 36 gs81302r36e-167 sigmaddr-ii b4 sram 165-bump bga 167 c 4m x 36 gs81302r36e-333i sigmaddr-ii b4 sram 165-bump bga 333 i 4m x 36 gs81302r36e-300i sigmaddr-ii b4 sram 165-bump bga 300 i 4m x 36 gs81302r36e-250i sigmaddr-ii b4 sram 165-bump bga 250 i 4m x 36 gs81302r36e-200i sigmaddr-ii b4 sram 165-bump bga 200 i 4m x 36 gs81302r36e-167i sigmaddr-ii b4 sram 165-bump bga 167 i 16m x 8 gs81302r08ge-333 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 333 c 16m x 8 gs81302r08ge-300 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 300 c 16m x 8 gs81302r08ge-250 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 250 c 16m x 8 gs81302r08ge-200 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 200 c 16m x 8 gs81302r08ge-167 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 167 c 16m x 8 gs81302r08ge-333i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 333 i 16m x 8 gs81302r08ge-300i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 300 i 16m x 8 gs81302r08ge-250i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 250 i 16m x 8 gs81302r08ge-200i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 200 i 16m x 8 gs81302r08ge-167i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 167 i 16m x 9 gs81302r09ge-333 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 333 c 16m x 9 gs81302r09ge-300 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 300 c 16m x 9 gs81302r09ge-250 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 250 c 16m x 9 gs81302r09ge-200 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 200 c 16m x 9 gs81302r09ge-167 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 167 c 16m x 9 gs81302r09ge-333i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 333 i 16m x 9 gs81302r09ge-300i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 300 i 16m x 9 gs81302r09ge-250i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 250 i 16m x 9 gs81302r09ge-200i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 200 i 16m x 9 gs81302r09ge-167i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 167 i 8m x 18 gs81302r18ge-333 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 333 c 8m x 18 gs81302r18ge-300 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 300 c 8m x 18 gs81302r18ge-250 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 250 c 8m x 18 gs81302r18ge-200 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 200 c ordering information?gsi sigmaddr-ii sram org part number1 type package speed (mhz) t a 2 notes: 1. for tape and reel add the character ?t? to the end of the part number. example: gs81302r36e-300t. 2. c = commercial temperature range. i = industrial temperature range.
preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 35/36 ? 2007, gsi technology 8m x 18 gs81302r18ge-167 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 167 c 8m x 18 gs81302r18ge-333i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 333 i 8m x 18 gs81302r18ge-300i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 300 i 8m x 18 gs81302r18ge-250i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 250 i 8m x 18 gs81302r18ge-200i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 200 i 8m x 18 gs81302r18ge-167i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 167 i 4m x 36 gs81302r36ge-333 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 333 c 4m x 36 gs81302r36ge-300 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 300 c 4m x 36 gs81302r36ge-250 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 250 c 4m x 36 gs81302r36ge-200 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 200 c 4m x 36 gs81302r36ge-167 sigmaddr-ii b4 sram rohs-compliant 165-bump bga 167 c 4m x 36 gs81302r36ge-333i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 333 i 4m x 36 gs81302r36ge-300i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 300 i 4m x 36 gs81302r36ge-250i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 250 i 4m x 36 gs81302r36ge-200i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 200 i 4m x 36 gs81302r36ge-167i sigmaddr-ii b4 sram rohs-compliant 165-bump bga 167 i ordering information?gsi sigmaddr-ii sram org part number1 type package speed (mhz) t a 2 notes: 1. for tape and reel add the character ?t? to the end of the part number. example: gs81302r36e-300t. 2. c = commercial temperature range. i = industrial temperature range.
revision history rev. code: old; new types of changes fo rmat or content revisions gs81302rxx_r1 format ? creation of new datasheet gs81302rxx_r1.00a content ? corrected ordering information table gs81302rxx_r1.01 content ? revised four bank depth expansion schematic ? revised power up information ? updated ac characteristics table ? updated 165 bga package drawing ? updated jtag operating port information ? (rev1.01a: removed cq reference from sample-z section in jt ag t ap instruction set summary) preliminary gs81302r08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 36/36 ? 2007, gsi technology

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